1. Field of the Invention
The present invention relates to an image processing apparatus and, more particularly, to a digital image signal processing apparatus.
2. Related Background Art
In a prestage of A/D conversion for performing digital signal processing, an input signal must be clamped to obtain a stable, accurate digital signal. Various types of conventional clamp schemes are available. A digital feedback clamp scheme is known as a clamp scheme for obtaining a stable signal almost free from temperature drifts and influences caused by variations in power source voltage.
FIG. 4 shows an arrangement of a conventional digital feedback clamp circuit. An operation of the conventional digital feedback clamp circuit will be described with reference to FIG. 4.
An input analog video signal is converted into a digital signal by an A/D (Analog-to-Digital) converter 10, and the digital signal is input to a comparator 12 through a latch circuit 11. The comparator 12 compares output data from the latch circuit 11 with reference data and outputs a comparison result. For example, if the reference data is set to be 01H (hexadecimal notation), when an output from the latch circuit 11 is 00H, an output from the comparator 12 goes to "H" (high level) to increase the clamp level. However, if the output form the comparator 12 is 01H, the output from the comparator 12 is set in a high-impedance state, thereby maintaining the present clamp level. If the output from the latch circuit 11 is 02H or more, the output from the comparator 12 goes to "L" (low level), thereby decreasing the clamp level.
A clamp gate circuit 13 outputs an output from the comparator 12 at a timing of a clamp pulse shown in FIG. 2B. An output from the clamp gate circuit 13 contains noise from a digital circuit. This noise is cut off by a low-pass filter (LPF) 14 to obtain a stable DC (Direct Current) level. The clamp level of an output from the LPF 14 is input to a clamp switch circuit 16 through a buffer 15. The clamp switch circuit 16 clamps the input signal (i.e., the analog video signal) in accordance with a pulse similar to the clamp pulse of the clamp gate circuit 13. The pedestal portion of the input analog video signal is kept at a predetermined level by the above operations, thereby performing a stable clamp operation.
In the conventional digital feedback clamp circuit described above, however, since comparison is performed by the comparator after the input signal is converted into the digital signal by the A/D converter, an error of about .+-.1 LSB corresponding to the least significant bit upon digital conversion occurs due to noise superposed on the input signal and quantization noise during A/D conversion. For this reason, when digital processing is to be performed with a smaller number of gradation bits caused by a reduction in memory capacity, one bit has a significant meaning. Even if digital feedback clamp is performed, the input signal as a whole varies within the range of .+-.1 bit. Therefore, digital processing with high precision cannot be performed, resulting in inconvenience.